`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/05 22:26:46
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    clk,reset_n,data,addr_ir
    );

    input clk;
    input reset_n;
    output [31:0] data;

    output wire [31:0] addr_ir;
    wire [6:0] opcode;
    wire [2:0] funct3;
    wire [6:0] funct7;
    wire [4:0] rd;
    wire [4:0] rs1;
    wire [4:0] rs2;
    
    wire [2:0] op_imm;
    wire [11:0] imm_inst1;
    wire [6:0] imm_inst2;
    wire [4:0] imm_inst3;
    wire [19:0] imm_inst4;
    wire [31:0] sextend_imm;
    wire [31:0] data_imm;

    wire [31:0] data_mem;
    // wire [31:0] data;
    wire [31:0] data1;
    wire [31:0] data2;
    
    wire [1:0] op_rd;
    wire [1:0] op_pc;
    wire [2:0] op_alu;
    wire op_w;
    wire zero;

    register_pc register_pc(.clk(clk),.reset_n(reset_n),.op_pc(op_pc),.data(data),.addr_ir(addr_ir),.sextend_imm(sextend_imm),
    .zero(zero));
    mem_inst mem_inst(.clk(clk),.reset_n(reset_n),.addr(addr_ir),.opcode(opcode),.funct7(funct7),.funct3(funct3),.rs1(rs1),
    .rs2(rs2),.rd(rd),.imm_inst1(imm_inst1),.imm_inst2(imm_inst2),.imm_inst3(imm_inst3),.imm_inst4(imm_inst4));
    registers registers(.clk(clk),.reset_n(reset_n),.op_rd(op_rd),.rd(rd),.rs1(rs1),.rs2(rs2),.data(data),.data1(data1),.data2(data2),
    .addr_ir(addr_ir),.data_mem(data_mem));
    imm imm(.data2(data2),.imm_inst1(imm_inst1),.imm_inst2(imm_inst2),.imm_inst3(imm_inst3),.imm_inst4(imm_inst4),
    .op_imm(op_imm),.sextend_imm(sextend_imm),.data_imm(data_imm));
    alu alu(.data1(data1),.data2(data_imm),.data(data),.op_alu(op_alu),.zero(zero));
    cu cu(.opcode(opcode),.funct3(funct3),.funct7(funct7),.op_imm(op_imm),.op_rd(op_rd),.op_alu(op_alu),.op_w(op_w),
    .op_pc(op_pc));
    mem_data mem_data(.clk(clk),.reset_n(reset_n),.addr(data),.data_in(data2),.data_out(data_mem),.op_w(op_w));

endmodule
